1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structures having uniform punch-through tolerance and threshold voltage along the channel width of each transistor in the structures.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Development in semiconductor technology enables these power devices to operate with high reliability and performance. However, modern day instruments are now built at a miniaturized scale with low power consumption. These instruments, such as fast switching power supplies, high-frequency ballasts and various portable electronic products, all require power devices to operate under certain stringent requirements. Accordingly, special criteria have to be met in the design and manufacturing of these devices. One area that shows prominence is the fabrication of power metal oxide semiconductor field effect transistor (MOSFET) using trenched gates.
In a trenched gate MOSFET structures, intersecting trenches which define a plurality of cells are formed in a silicon substrate. The trenches are filled with conductive material separated from the silicon substrate with a thin layer of insulating material. There are also other diffusion layers, such as the channel and source layers, of different impurity types and concentration deposited in the semiconductor substrate. As arranged, the conductive and insulating materials in the trenches constitute the gate and gate oxide layer, respectively, of the MOSFET. In addition, the perimeter and the depth of the cell correspond to the respective channel width and depth of each MOSFET cell.
Power MOSFET with trenched gates provide many advantages. To begin with, the channels of the MOSFETs are arranged in a vertical manner, instead of horizontally as in most planar configurations. The consequential benefit is that a higher degree of integration on a semiconductor substrate can be realized. More importantly, since the channel direction is vertical, the lateral current paths, normally congestively packed, are basically eliminated. As a result, the overall channel resistance is reduced. Reduction in channel resistance substantially curtails the ohmic loss during the power-on state of the MOSFET, which in turn provides lower power consumption and further alleviates heat dissipation.
Advantageous as it appears, there are technical difficulties associated with the fabrication of such trenched MOSFET devices. One of such difficulties confronted by manufacturers is the problem of uneven punch-through tolerance along the channel width of a trenched gate MOSFET. To understand the underlying causes of the uneven punch-through problem associated with a MOSFET, the structure and operation of a conventional MOSFET cell need first be explained.
FIG. 1 shows two conventional trenched gate MOSFET cells 2 placed adjacent to each other in an cell array 4. The cells 2 share a common substrate 6. Formed in the substrate 6 are trenches 8 filled with conductive material 10 which is electrically separated from the substrate 6 by an insulating layer 12. The substrate 6 includes a base drain layer 20 epitaxially grown with an epitaxial layer 14. Deposited atop the expitaxial layer 14 is a body layer 16. There is also a source layer 18 diffused in the body layer 16. As arranged, the epitaxial layer 24 in conjunction with the heavily doped base drain layer 20 which is in contact with a drain metal layer 22 constitute the drain D of the MOSFET array 4. The source layer 18 in contact with the source metal layer 24 forms the source S of the array 4. The conductive material 10 inside the trenches 8 are connected together (not shown in FIG. 1) becomes the gate G of the array 4. As shown in FIG. 1, the source layer 18 does not have symmetrical source regions 18R and 18L along the line of symmetry 26 for each cell 2.
The reason for the asymmetrical disposition of the source regions 18R and 18L in the body region 16 stems from the conventional manufacturing process having no means of correction or compensation. During fabrication in a conventional process, after the trenches 8 are formed in the substrate 6 with the lined insulating material 12, the trenches 8 are filled with conductive material 10. To accomplish this end, the entire substrate 6 is covered with conductive material 10. Thereafter, the unwanted conductive material 10 is etched away such that the remaining conductive material 10 is barely within the trenches 8. The goal is to leave no residues left on the top surface 28 of the substrate 6. This step is crucial in the fabrication process because any residual conductive material 10 remaining on the substrate surface may cause electrical shorts for the subsequent overlying layers. As a safeguard, the conductive material 10 are normally somewhat over etched below the substrate surface 28. As shown in FIG. 2, the conductive material 10 is etched below the substrate surface 28 at a depth x as a margin of safety. To determine the value of the depth x, it needs to take into consideration of the different etch rates within a wafer (not shown) in which the multiplicity of cell arrays 4 are diced from. Very often, the areas closer to the center of the wafer assumes a higher etch rate than the areas near the edge of the wafer. The larger the area of the wafer, the more deviated is the value of the depth x. To maintain high production yield, the value of the depth x is normally set at a higher value. However, etching the depth x to a higher value consequently results in the asymmetrical disposition of the source layer 18 as is herein described.
The source layer 18 is formed by first ion-implanting the substrate 6 with a preselected source material and thereafter diffusing the implanted source material into the substrate 6. During ion-implantation of the source layer 18, the ion beam 30 needs to be skewed at an angle .alpha. with respect to the normal 32 to the substrate surface 28 as shown in FIG. 2. The chief reason for the skew orientation of the ion beam 30 is to avoid the channeling effect, which is briefly described here in conjunction with FIG. 3. A detailed analysis of the channeling effect can be found in Wolf et al., "Silicon Processing for the VLSI Era", Vol 1., Lattice Press, 1986, pages 292-294.
As is known in the art, to facilitate anisotropic etching of the trenches 8, the crystal orientation of the wafer is normally chosen to be orthogonal with respect to the substrate surface 28. If the skew angle .alpha. is zero, the ion beam 30 may theoretically encounter no crystal lattice reflection and travels unopposed through the wafer 34 as shown in FIG. 3. To predictably control the depth of the ion implant in the substrate 6, the ion beam 30 is commonly aimed at the angle .alpha. with respect to the wafer normal 32 during implantation. However, problems arise if the value of the depth x (FIG. 2) is too large.
As shown in FIG. 2, with the conductive material 10 etched below the substrate surface 28 at a depth x, substrate steps 86 with step height x are formed at the entry of the trenches 8. Prior to ion-implantation of the source layer 18, the substrate 6 is patterned with a photoresist mask 36 which eventually defines the various source segments 18R and 18L. With the ion beam 30 aiming at the wafer surface 28 at an angle .alpha., the exposed top portions T1 and T2 of the substrate steps 86 are implanted with source material at the right and left sides of the trench 8, respectively. In addition, the exposed sidewall portion W1 of the step 86 at the right side of the trench 8 having a depth x is also impregnated with source material. Subsequently, the implanted source material at regions T1, T2 and W1 simultaneously undergo a diffusion process in which the asymmetrical source regions 18R and 18L will result.
The presence of the asymmetrical source regions 18R and 18L around the trench gate 8 is undesirable in several aspects. First, the asymmetrical arrangement of the source segments 18L and 18R in the source layer 18 will cause asymmetrical current flow during normal operation. As shown in FIG. 2, because the source region 18R encroaches closer to the epitaxial layer 14 which is part of the drain D, the right side of the trench gate 8 has a channel length L.sub.R which is shorter than the left side of the channel length L.sub.L. Current always seeks the path with the lowest resistance to pass through. As a consequence, the right side of the MOSFET cell 2 is more crowded in current than the left side counterpart resulting in an uneven heat dissipation pattern on the array 4 as a whole. Furthermore, the asymmetrical source layer 18 also yields nonuniform threshold voltages along the channel width of each transistor 2, resulting in the threshold voltage of the entire MOSFET array 4 assuming a wide margin and is difficult to specify. However, most detrimental of all is the premature punch-through problem caused by the expanded source region 18R toward the epitaxial layer 14.
Returning to FIG. 2, during normal operation, the epitaxial layer 14 and the body layer 16 are reversely biased. As such, a depletion region 38 is formed at the common boundary of the layers 14 and 16 with an overall depletion width W. Since the body layer 16 has a higher impurity concentration than the epitaxial layer 14, the portion of the depletion region 38 is wider at the epitaxial layer 14 than the corresponding portion at the body layer 16. At still higher reverse bias potential, a point may be reached whereby the depletion region 38 merges with the source region 18R. The MOSFET cell 2 is said to be at the state of punch-through. During punch-through, current traverses directly through the source layer 18 and the drain D via the epitaxial layer 14 with no control whatsoever by gate G (FIG. 1). A MOSFET incapable of being controlled by the gate G is a malfunctioning MOSFET.
Attempts have been made to tackle the premature punch-through problem in a trenched MOSFET. Disclosed in U.S. Pat. No. 5,468,982, Hshieh et al., entitled "Trenched DMOS Transistor with Channel Block at Cell Trench Corners", issued Nov. 21, 1995, is a trenched gate MOSFET with the MOSFET cell corner regions completely blocked off. In the '982 patent, cell corners of the source implant mask are covered during the deposition of the source layer, thereby avoiding the formation of the MOSFET at the corner regions. However, with this approach, the channel width, which is defined as the cell perimeter length as mentioned above, is also consequently shortened. A shortened channel width increases the overall channel resistance R.sub.ON.
Instruments are now built with ever increasing complexity and decreasing physical sizes. To satisfy the stringent requirements demanded of these instruments, reliable power devices with high performance need to be provided. Specifically, the power devices need to exhibit ruggedness in performance with predictable operating ranges. At the same time, production yield and manufacturing costs also need to be controlled. There has been a long-felt and increasing need to provide power devices meeting the aforementioned criteria.